1. Field of the Invention
The present invention relates to an automatic cell placement method in which cells to be arranged in a semiconductor integrated circuit are automatically placed so as to shorten a total length of signal wires connecting the cells with each other.
2. Description of Related Art
As the number of cells (or electronic circuits) arranged in a semiconductor integrated circuit is increased, the influence of signal delay caused in signal wires on the circuits becomes important. In cases where intervals of signal wires connecting the cells with each other become shorter than 0.25 gm, the signal delay caused in signal wires becomes longer than the signal delay caused in transistors. Because the signal delay caused in a signal wire is in proportion to a signal wire length squared, it is required to shorten lengths of signal wires for the purpose of decreasing the signal delay caused in the signal wires.
In a conventional automatic cell placement and route method used for the manufacturing of a semiconductor integrated circuit, Min-Cut Placement (Melvin A. Breuer, xe2x80x9cMin-Cut Placementxe2x80x9d, Journal of Design Automation and Fault Tolerant Computing, Vol.1, No.4, pp.343-362, October 1977) is widely used in a cell placing process as a conventional automatic cell placement method.
In the Min-Cut Placement, a placement area of a plurality of cells, which are connected with each other through signal wires, is repeatedly divided into two parts along a cut line. In this case, each of the cells is placed in one of two divided placement areas to minimize the number of signal wires crossing the cut line. More precisely, in cases where two or more cells are placed in each of the two divided placement areas, each divided placement area is again divided into two parts along another cut line. In cases where two or more cells are placed in one of the two divided placement areas and only one cell is placed in the other divided placement area, only the divided placement area having two or more cells is again divided into two parts along another cut line. Also, in cases where only one cell is placed in each of the two divided placement areas, the division of each divided placement area is not performed any more. That is, the division of the divided placement area is repeated until the number of cells placed in the divided placement area reaches 1, and the placement area of the cells is finally divided into a plurality of minimum placement areas respectively having one cell.
Therefore, in the Min-Cut Placement, in cases where the number of signal wires connecting a plurality of particular cells with each other is large, the minimum placement areas of the particular cells are closely placed. In contrast, in cases where the number of signal wires connecting a plurality of particular cells with each other is small or zero, the minimum placement areas of the particular cells are placed far from each other. Accordingly, a total length of the signal wires can be shortened.
FIG. 5A shows a plurality of cells placed in a cell placement area, and FIG. 5B to FIG. 5E show the cell placement areas respectively divided along one cut line or a plurality of cut lines according to the Min-Cut Placement. In FIG. 5A to FIG. 5E, 101 indicates a first cell, 102 indicates a second cell, 103 indicates a third cell, 104 indicates a signal wire connecting each pair of cells with each other, 105 indicates a cell placement area, 106 indicates a minimum cell placement area obtained by repeatedly dividing the cell placement area 105, C101 indicates a first cut line, C102 indicates a second cut line, C103 indicates a third cut line, C104 indicates a fourth cut line, C105 indicates a fifth cut line, and C106 indicates a sixth cut line.
As shown in FIG. 5B, the cell placement area 105 shown in FIG. 5A is divided along the cut line C101, the cells 101 and 102 are placed in a divided cell placement area, and the cell 103 is placed in another divided cell placement area. As shown in FIG. 5C, each of the cell placement areas shown in FIG. 5B is divided along the cut line C102, and the cells 101, 102 and 103 are respectively placed in a divided cell placement area. As shown in FIG. 5D, each of two upper cell placement areas shown in FIG. 5C is divided along the cut line C103 into two parts to place cells (not shown) in each of divided upper cell placement areas, and each of two lower cell placement areas shown in FIG. 5C is divided along the cut line C104 into two parts to place cells (not shown) in each of divided lower cell placement areas. As shown in FIG. 5E, each of four left cell placement areas shown in FIG. 5D is divided along the cut line C105 into two parts to place a cell (not shown) in each of minimum left cell placement areas 106, and each of four right cell placement areas shown in FIG. 5D is divided along the cut line C106 into two parts to place a cell (not shown) in each of minimum right cell placement areas 106.
As is described above, in the Min-Cut Placement, because a placement area of a plurality of cells is repeatedly divided into two parts along a cut line to place only one cell in each divided placement area while minimizing the number of signal wires crossing the cut line every division, the Min-Cut Placement is useful for the manufacturing of a semiconductor integrated circuit in which a plurality of electronic circuits are arranged only on a single semiconductor chip.
However, as is disclosed in the U.S. Pat. No. 5,923,091, in cases where a semiconductor integrated circuit is manufactured by attaching two semiconductor chips to each other to make electronic circuits arranged on one semiconductor chip face electronic circuits arranged on the other semiconductor chip, because the group of electronic circuits of the semiconductor chips of the semiconductor integrated circuit is not arranged in one plane, there is a problem that the Min-Cut Placement is not appropriate for the manufacturing of the semiconductor integrated circuit in which electronic circuits arranged on one semiconductor chip face electronic circuits arranged on the other semiconductor chip. This type of semiconductor integrated circuit is described with reference to FIG. 6A to FIG. 6D.
FIG. 6A is a plan view showing a plurality of cells (or electronic circuits) arranged on a first semiconductor chip of a semiconductor integrated circuit, FIG. 6B is a plan view showing a plurality of cells (or electronic circuits) arranged on a second semiconductor chip of the semiconductor integrated circuit, FIG. 6C is a plan view showing the semiconductor integrated circuit in which the first and second semiconductor chips are attached to each other so as to make the cells of the first semiconductor chip face the cells of the second semiconductor chip, and FIG. 6D is a cross sectional view taken substantially along line Xxe2x80x94X of FIG. 6C. In FIG. 6A to FIG. 6D, 13 indicates a first semiconductor chip, 14 indicates a second semiconductor chip, 1 indicates a first cell arranged on the first semiconductor chip 13, 2 indicates a second cell arranged on the first semiconductor chip 13, 3 indicates a third cell arranged on the second semiconductor chip 14, 4 indicates a fourth cell arranged on the second semiconductor chip 14, 9 indicates an input/output pin of the first cell 1, 10 indicates an input/output pin of the second cell 2, 11 indicates an input/output pin of the third cell 3, 12 indicates an input/output pin of the fourth cell 4, 15 indicates a signal wire connecting the input/output pin 10 of the second cell 2 and the input/output pin 12 of the fourth cell 4, and 16 indicates each of a plurality of bonding pads arranged in the peripheral area of the first semiconductor chip 13.
As shown in FIG. 6A to FIG. 6D, the first semiconductor chip 13, on which a first group of cells including the cells 1 and 2 is arranged, is formed, the second semiconductor chip 14, on which a second group of cells including the cells 3 and 4 is arranged, is formed, and the first semiconductor chip 13 and the second semiconductor chip 14 are attached to each other to make the first group of cells face the second group of cells. Therefore, the semiconductor integrated circuit disclosed in the U.S. Pat No. 5,923,091 is manufactured. Also, in this semiconductor integrated circuit, the input/output pin 9 of the first cell 1 is directly connected with the input/output pin 11 of the third cell 3 (refer to FIG. 6D), and the input/output pin 10 of the second cell 2 is connected with the input/output pin 12 of the fourth cell 4 through the signal wire 15. Therefore, no signal wire connecting the input/output pin 9 of the first cell 1 and the input/output pin 11 of the third cell 3 is required because the first cell 1 and the third cell 3 are arranged to make the first cell 1 face the third cell 3. Also, though the second cell 2 does not face the fourth cell 4, the signal wire 15 connecting the second cell 2 and the fourth cell 4 can be shortened as compared with a case where the first semiconductor chip 13 and the second semiconductor chip 14 are arranged not to make the group of cells of the first semiconductor chip 13 face the group of cells of the second semiconductor chip 14.
In general, to efficiently shorten a total length of signal wires in the semiconductor integrated circuit, it is preferred that a plurality of particular cells are preferentially arranged to face each other in cases where the number of signal wires connecting the particular cells with each other is large.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional automatic cell placement method, an automatic cell placement method in which cells to be arranged in a semiconductor integrated circuit, in which a first semiconductor chip and a second semiconductor chip are attached to each other to make a first cell group of the first semiconductor chip face a second cell group of the second semiconductor chip, are automatically placed so as to efficiently shorten a total length of signal wires used in the semiconductor integrated circuit.
The object is achieved by the provision of an automatic cell placement method comprising the steps of:
dividing a plurality of cells to be arranged in a semiconductor integrated circuit into cells of a first cell group and cells of a second cell group so as to maximize the number of inter-group signal wires respectively connecting one cell of the first cell group and one cell of the second cell group;
allocating the cells of the first cell group to a first semiconductor chip;
allocating the cells of the second cell group to a second semiconductor chip;
placing the cells of the first cell group in the first semiconductor chip, placing the cells of the second cell group in the second chip, and attaching the first semiconductor ship and the second semiconductor chip to each other to make the first cell group of the first semiconductor chip face the second cell group of the second semiconductor chip.
In the above steps, the cells to be arranged in the semiconductor integrated circuit are divided into the first cell group and the second cell group so as to maximize the number of inter-group signal wires.
Accordingly, in cases where the cells are placed to shorten, a total length of the inter-group signal wires, because the number of inter-group signal wires is maximized, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened. Thus, the adverse influence of signal delay caused in the signal wires of the semiconductor integrated circuit can be considerably reduced. Therefore, the automatic cell placement method of the present invention is appropriate for the semiconductor integrated circuit in which the first semiconductor chip and the second semiconductor chip are attached to each other to make the cells of the first semiconductor chip face the cells of the second semiconductor chip.
It is preferred that the step of placing the cells comprises the steps of:
determining the placement of the cells of the first cell group;
preparing position information indicating positions of the cells of the first cell group of which the placement is determined;
preparing number information of the first cell group which indicates the number of inter-group signal wires connecting each of the cells of the first cell group and one or more corresponding cells of the second cell group; preparing number information of the second cell group which indicates the number of intergroup signal wires connecting each of the cells of the second cell group and one or more corresponding cells of the first cell group; and
determining the placement of the cells of the second cell group according to the position information, the number information of the first cell group and the number information of the second cell group.
In the above steps, because the placement of the cells of the second cell group is determined according to the position information of the cells of the first cell group and the number information of the first and second cell groups, the cells of the second cell group can be placed so as to shorten a total length of the inter-group signal wires. Therefore, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened.
It is also preferred that the step of determining the placement of the cells of the second cell group includes the step of:
placing the cells of the second cell group so as to minimize a total length of the inter-group signal wires respectively connecting one cell of the first cell group and one cell of the second cell group.
Because each of the cells of the second cell group are placed so as to minimize a total length of the inter-group signal wires, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened.
It is also preferred that the step of determining the placement of the cells of the second cell group comprises the step of:
placing one or more particular cells of the second cell group, which are to be connected with a particular cell of the first cell group, so as to be directly connected with the particular cell of the first cell group in the semiconductor integrated circuit; and
placing the other particular cells of the second cell group, which are to be connected with the particular cell of the first cell group, so as to be arranged near the particular cell of the first cell group in the semiconductor integrated circuit.
In the above steps, because the particular cells of the second cell group are placed to be directly connected with the particular cell of the first cell group in the semiconductor integrated circuit, no inter-group signal wire connecting each particular cell of the second cell group and the particular cell of the first cell group is required. Also, because the other particular cells of the second cell group are placed to be arranged near the particular cell of the first cell group in the semiconductor integrated circuit, the inter-group signal wire connecting each of the other particular cells of the second cell group and the particular cell of the first cell group can be considerably shortened. Therefore, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened.
It is also preferred that the step of determining the placement of the cells of the first cell group includes the step of:
placing the cells of the first cell group so as to minimize a total length of inner-group signal wires respectively connecting one pair of cells of the first cell group, and
the step of determining the placement of the cells of the second cell group includes the step of:
placing the cells of the second cell group so as to minimize a total length of inner-group signal wires respectively connecting one pair of cells of the second cell group.
In the above steps, because the total length of the inner-group signal wires in the first and second cell groups is minimized, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened.
The object is also achieved by the provision of an automatic cell placement method comprising the steps of:
dividing a plurality of cells to be arranged in a semiconductor integrated circuit into a plurality of cell blocks respectively having two cells or three cells to minimize the number of inter-block signal wires respectively connecting one cell of one cell block and one cell of another cell block;
allocating one of the two cells or one or two of the three cells existing in each cell block to a first semiconductor chip to form a first cell group of the first semiconductor chip;
allocating the other one cell of the two cells or the other one or the other two cells of the three cells existing in each cell block to a second semiconductor chip to form a second cell group of the second semiconductor chip;
placing the cells of the first cell group and the cells of the second cell group in the first semiconductor chip and the second semiconductor chip respectively, and attaching the first semiconductor chip and the second semiconductor chip to each other to make the first cell group of the first semiconductor chip face the second cell group of the second semiconductor chip.
In the above steps, the cells to be arranged in the semiconductor integrated circuit are divided into a plurality of cell blocks to minimize the number of interblock signal wires. One of the two cells or one or two of the three cells existing in each cell block is/are allocated to the first semiconductor chip. The other one cell of the two cells or the other one or the other two cells of the three cells existing in each cell block is/are allocated to the second semiconductor chip to form a second cell group. Because the number of inter-block signal wires is minimized, the number of intra-block signal wires connecting one of the two cells and the other cell in each cell block or connecting one or two of the three cells and the other one or the other two cells in each cell block can be maximized.
Accordingly, in cases where the cells of the first cell group and the cells of the second cell group are placed so as to shorten a total length of the inter-block signal wires, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened. The adverse influence of signal delay cause in the signal wires of the semiconductor integrated circuit can be considerably reduced. Therefore, the automatic cell placement method of the present invention is appropriate for the semiconductor integrated circuit in which the first semiconductor chip and the second semiconductor chip are attached to each other to make the cells of the first semiconductor chip face the cells of the second semiconductor chip.
It is preferred that the step of placing the cells includes the step of determining the placement of the cells of the first cell group in the first semiconductor chip, and determining the placement of the cells of the second cell group in the second semiconductor chip.
It is also preferred that the step of determining the placement of the cells of the second cell group includes the step of:
placing the cells of the second cell group so as to minimize a total length of the inter-group signal wires respectively connecting one cell of the first cell group and one cell of the second cell group.
Because each of the cells of the second cell group are placed so as to minimize a total length of the inter-group signal wires, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened.
It is also preferred that the step of determining the placement of the cells of the second cell group comprises the step of:
placing one or more particular cells of the second cell group, which are to be connected with a particular cell of the first cell group, so as to be directly connected with the particular cell of the first cell group in the semiconductor integrated circuit; and
placing the other particular cells of the second cell group, which are to be connected with the particular cell of the first cell group, so as to be arranged near the particular cell of the first cell group in the semiconductor integrated circuit.
In the above steps, because the particular cells of the second cell group are placed to be directly connected with the particular cell of the first cell group in the semiconductor integrated circuit, no inter-group signal wire connecting each particular cell of the second cell group and the particular cell of the first cell group is required. Also, because the other particular cells of the second cell group are placed to be arranged near the particular cell of the first cell group in the semiconductor integrated circuit, the inter-group signal wire connecting each of the other particular cells of the second cell group and the particular cell, of the first cell group can be considerably shortened. Therefore, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened.
It is also preferred that the step of determining the placement of the cells of the first cell group includes the step of:
placing the cells of the first cell group so as to minimize a total length of intra-group signal wires respectively connecting one pair of cells of the first cell group, and
the step of determining the placement of the cells of the second cell group includes the step of:
placing the cells of the second cell group so as to minimize a total length of intra-group signal wires respectively connecting one pair of cells of the second cell group.
In the above steps, because the total length of the intra-group signal wires in the first and second cell groups is minimized, a total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened.
It is also preferred that the step of dividing a plurality of cells includes the step of:
dividing three cells of one cell block into one cell and a set of two cells to maximize the number of signal wires respectively connecting the cell and the set of two cells in cases where the cell block has the three cells.
In the above step, in cases where the cell block has the three cells, because the one cell of the cell block is allocated to the first or second semiconductor chip and the set of two cells of the cell block is allocated to the other semiconductor chip, the number of inter-group signal wires respectively connecting one cell of the first cell group and one cell of the second cell group can be maximized. A total length of signal wires used in the semiconductor integrated circuit can be efficiently shortened by shortening the total length of the inter-group signal wires.